1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device having a self-aligned structure.
2. Description of the Prior Art
Y. Kobayashi et al. published "High Speed IC fabricated by SST4 process" in the 1986 National Meeting of the Institute of Electronics and Communication Engineers of Japan. This publication relates to an improvement of an SST (super self-aligned process technology) structure. Specifically, the improved SST structure additionally has a collector compensation layer. According to this publication, in a fabricated transistor, an emitter width was equal to 0.35 .mu.m and the distance between a collector and an emitter was equal to 0.65 .mu.m, and the distance between the emitter and a base was also equal to 0.65 .mu.m.
M. Suzuki et al. published "A 165 ps/gate 5000-Gate ECL Gate Array" in Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 377-380. According to this publication, a 5130-gate ECL gate array has been developed with a basic gate delay of 164 ps/gate at a power dissipation of 1.5 mW/gate. This gate array is fabricated by using 1.5 .mu.m rule super self-aligned process technology (SST-1A) combined with deep U-groove isolation and three-level metallization technology. This device permits the customization of a dual 40-bit data link control LSI equivaling 3654 gates for the multiprocessing system. The power dissipation of this LSI is 4.8 W/chip.
U.S. Pat. No. 4,693,782 discloses a method of fabricating a semiconductor device having the structure of self-alignment between an emitter contact and a base contact.
U.S. Pat. No. 4,908,324 discloses a method of manufacturing a bipolar transistor having the structure of self-alignment between an emitter contact and a base contact.
FIG. 1 shows a transistor with the base and the emitter formed by a self-aligned process which is published in the 1983 National Meeting of the Semiconductor Material Department of the Institute of Electronics and Communication Engineers of Japan.
As shown in FIG. 1, the prior art transistor includes a p-type semiconductor substrate 1, an n-type buried layer 2, an n-type epitaxial layer 3, an isolating region 4 consisting of an SiO.sub.2 film, a base diffusion layer 5, an emitter lead-out electrode 9 consisting of a polycrystalline silicon film containing arsenic, a collector lead-out electrode 10 consisting of a polycrystalline silicon film containing arsenic, a base lead-out electrode 13 consisting of a polycrystalline silicon film containing boron, an emitter diffusion layer 15, a base contact diffusion layer 16, a collector contact diffusion layer 17, electrode leads 21-23 of aluminum or the like, SiO.sub.2 films 50, 52, and 53, an Si.sub.3 N.sub.4 film 51, and an emitter contact 100.
In the prior art transistor of FIG. 1, the base and the emitter are formed by a self-aligned process. During the self-aligned process, the base electrode 13 is formed, and then an SiO.sub.2 film is formed. The SiO.sub.2 film is subjected to an anisotropic dry etching process to leave the SiO.sub.2 film 53 on a side surface of the base electrode 13. In addition, an opening for the emitter contact 100 is provided in the SiO.sub.2 film. The self-aligned process enables smaller emitter and base, thus reducing the emitter-base capacitance, the base-collector capacitance, and the base resistance. The reductions of these parameters result in a higher operation speed of the transistor.